1. Field of the Invention
The present invention relates to an apparatus and method for driving a plasma display panel (PDP), and more particularly, to an energy recovery apparatus and method for recovering energy in a PDP at improved efficiency using a single energy storage device and a small number of devices regardless of the number of pixels that become conductive as a result of the screen state.
2. Description of the Related Art
A PDP is a next generation display apparatus, which displays characters and images using plasma that is generated due to gas discharge. A PDP includes hundreds of thousands to millions of pixels in a matrix, depending on its size.
A sequence of driving a PDP is divided into a reset period, an address period, and a sustain period. During the reset period, all cells are discharged and simultaneously wall charges are eliminated, so that hysteresis regarding the display is eliminated. During the address period, an address discharge is performed in cells selected according to a matrix structured by combining row and column electrodes of the PDP. During the sustain period, an image is displayed while a discharge, determined for each cell during a scan period, alternates with energy recovery.
During the address period and the sustain period, an energy recovery apparatus is used in order to reduce power consumption.
FIG. 1 shows a conventional energy recovery apparatus used for a PDP during the address period. In other words, FIG. 1 shows a conventional energy recovery apparatus applied to an address driving circuit 100 of a PDP. In a PDP, each column electrode can be assumed to carry a load of capacitance Ca. During the address period, a load is represented with a variable load from 0 to nCa (where “n” is the number of pixels turned on per electrode row, i.e., an address electrode). An address energy recovery operation performed by an energy storage device, i.e., a capacitor C1, and an inductor L1 can be divided into four modes as follows. The four modes will be described with reference to a switch timing chart and waveform diagrams shown in FIGS. 2A through 2H.
1) Mode 1 (M1)
Before a MOSFET switch S1 is turned on, a switch S4 is turned on and voltage at both ends of each address electrode is sustained at Vp=Vo(1)=Vo(2)= . . . =Vo(n)=0. When the switch S1 is turned on at the beginning of a time period t0, mode 1 (M1) starts. During mode 1, an LC resonance circuit is formed on a path C1-S1-D1-L1-Su (pixel to be conducted)-Ca (pixel to be conducted). Accordingly, resonance current flows in the inductor L1, and thus an address electrode voltage Vp increases. At the beginning of a time period t1, the current of the inductor L1 is 0 A, and Vp=+Va.
2) Mode 2 (M2)
At the beginning of the time period t1, a switch S3 is turned on. During mode 2 (M2), Vp=+Va, and wall charges are accumulated in each address electrode depending on the conditions of an image.
3) Mode 3 (M3)
At the beginning of a time period t2, a switch S2 is turned on, and the switches S1 and S3 are turned off. Accordingly, during mode 3 (M3), an LC resonance circuit is formed on a path Ca (pixel to be conducted)-Su (pixel to be conducted)-L1-D2-S2-C1, resonance current flows in the inductor L1, and the voltage Vp decreases. At the beginning of a time period t3, the current of the inductor L1 is 0 A, and Vp=0.
4) Mode 4 (M4)
At the beginning of a time period t3, the switch S4 is turned on. During mode 4 (M4), Vp=0. When the switches S2 and S4 are turned off and the switch S1 is turned on at the beginning of a time period t4, another cycle starts.
Here, the value of the inductor L1 for energy recovery is determined by the following formula.   L1  =                              (                                    t              2                        +                          t              4                                )                2                    4        ⁢                                   ⁢                  π          2                ⁢        n        ⁢                                   ⁢        Ca              .  
For example, when t2+t4=200 ns, Ca=66.5 pF, and n=1248 (the number of address electrodes of a high-definition (HD) PDP), the value of the inductor L1 for satisfactory energy recovery is 12.2 nH according to the above formula. However, an inductance value below 100 nH is difficult to realize because of, for example, the leakage inductance of a printed circuit board (PCB). When the value of the inductor L1 is set to about 100 nH, and “n” is large, as shown in FIG. 2H, a voltage rapidly changes by Vst. As a result, address energy cannot be recovered. In order to solve this problem, a plurality of address energy recovery apparatuses, each similar to the one shown in FIG. 1, must be used. However, use of the plurality of address energy recovery apparatuses increases the number of components in a PDP driving system, thereby increasing manufacturing cost. In addition, the number of signal lines increases, causing PCB design to become very complicated.